Paper Submission



Author Guidelines

Paper Submission: Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words. Previously published papers or papers currently under review for other conferences/journals should NOT be submitted and will not be considered. To enable blind review, the author list should be omitted from the main document. The manuscript as a single PDF is to be submitted online through Easychair. The IEEE Manuscript Template for Conference Proceedings should be used, which can be found here: (Link to Template).



Papers are encouraged to target one of the following program tracks:

  • Circuits, Reliability, and Fault-Tolerance (CRT):
    Analog/mixed-signal circuits design and testing, RF and communication circuits, adaptive circuits and interconnects, design for testability, online testing techniques, static and dynamic defect- and fault- recoverability, variation aware design, VLSI aspects of sensor and sensor network.
  • Computer-Aided Design and Verification (CAD):
    Hardware/software co-design, logic and behavioral synthesis, simulation and formal verification, physical design, signal integrity, power and thermal analysis, statistical approaches.
  • Digital Circuits and FPGA based Designs (DCF):
    Digital circuits, chaos/neural/fuzzy-logic circuits, high speed/low-power circuits, energy efficient circuits, near and sub-threshold circuits, memories, FPGA designs, FPGA based systems.
  • Emerging and Post-CMOS Technologies (EPT):
    Nanotechnology, molecular electronics, quantum devices, optical computing, spin-based computing, biologically-inspired computing, CNT, SET, RTD, QCA, reversible logic, and CAD tools for emerging technology devices and circuits.
  • System Design and Security (SDS):
  • Structured and custom design methodologies, microprocessors/micro-architectures for performance and low power, embedded processors, analog/digital/mixed-signal systems, NoC, power and temperature aware designs, hardware security, cryptography, watermarking, and IP protection, TRNG and security-oriented circuits, PUF circuits.
  • VLSI for Applied and Future Computing (AFC):
    Neuromorphic and brain-inspired computing, quantum computing, circuits and architectures for machine learning and artificial intelligence, methodologies for on-chip learning, deep learning acceleration techniques, applications for and use-cases of learning systems, sensor and sensor network, electronics for Internet of Things and smart medical devices.



Organization

General Chairs:
Nikolaos Voros, University of Peloponnese, Greece
Michael Huebner, Brandenburgische Technische Universität Cottbus-Senftenberg, Germany

TPC Chairs:
Georgios Keramidas, Aristotle University of Thessaloniki, Greece
Paraskevas Kitsos, University of Peloponnese, Greece
Diana Goehringer, Technical University of Dresden, Germany

Steering Committee:
Juergen Becker (chair)
Saraju Mohanty (vice-chair)
Hai (Helen)Li
Lionel Torres
Michael Hübner
Nikolaos Voros
Ricardo Reis
Sandip Kundu
Sanjukta Bhanja
Susmita Sur-Kolay
Theocharis Theocharides
Vijay Narayanan

Contact Us

Michael Huebner - Michael.Huebner@b-tu.de
Nikolaos Voros - voros@go.uop.gr