Abstract:

The talk will cover the trends of microelectronics/VLSI technologies towards the 6G wireless communication evolution covering both FR2 and FR3 frequency bands.  It will exploit the full potential of best-in-class Silicon CMOS and SiGe BiCMOS, InP and heterogeneous 3D integration for high capacity radio access technologies and applications such as wireless back-hauling at sub-THz frequencies, Joint Communication and Sensing, Non Terrestrial Networks and Network as a Sensor. We will present new classes of chipsets that will unleash the full potential of 6G and enable the emergence of new applications through specific developments for the underpinning novel microelectronic technologies.  The talk will also valorize resource efficient 6G algorithms and an ML/AI toolbox for computationally efficient silicon-ready baseband extensions by integrating RISC-V architectures and various chiplet solutions. New baseband processing and advanced beamforming VLSI circuits are very important not only for the FR2 frequency band but also for the FR3 frequency band, seen lately as a promising space to address the ‘empty pipe problem’ of telecom operators and push 6G evolution.

Abstract:

Digital integrated circuits and embedded memories play an important role in the energy, performance, reliability and cost targets of almost all electronic devices and silicon-based systems. Over the last four decades, conventional Static CMOS logic and embedded Static RAMs (SRAMs) have become the dominant design methodologies and are now widely used in the semiconductor industry.

In the past, dynamic operation-based logic, such as Domino logic, and embedded dynamic memories (eDRAMs) were proposed and utilized as alternatives to static counterparts. Although classical dynamic circuits promised substantial performance improvements for logic and area reduction for memories, their reliable design in nanoscale CMOS processes became very challenging, resulting in their abandonment in industrial applications.

This talk will explore the potential for a resurgence of dynamic operation in logic and embedded memories using conventional nanoscale CMOS technologies Specifically, Professor Fish will demonstrate how design methodologies, such as Dual Mode Logic (DML), can enhance performance, energy efficiency, and area utilization. He will also discuss how modern Gain-Cell (GCRAM) dynamic embedded memory technology can reliably provide up-to 50% silicon area reduction and up-to 10X reduced power consumption over SRAM, using standard CMOS fabrication flow. Finally, Professor Fish will present the advantages of cryogenic operation of dynamic circuits in the context of high-performance computing and quantum applications.

Abstract:

The end of Moore's Law and physical constraints from random defects on silicon wafers limit the die size and subsequently the achievable computing performance of a single chip die. Tightly integration of multiple chip dies (Chiplets) on a single package helps overcome these limitations, offering scalable performance, higher silicon yield, lower cost, and design flexibility. Utilizing chiplets enable the development of complex custom chips by combining various existing and new chiplets for common and custom functions (mix and match).

Additionally, third-party specialized chiplets, such as high-speed memory, CPUs, and common peripherals, transform into chiplet products, facilitating rapid development and significantly lowering the overall NRE cost of large custom chips.

Although the concept began in the early 2000s, transitioning from multi-chip modules to advanced packaging took over two decades. The lack of efficient chip-to-chip interface standards has limited the wider adoption of multi-vendor chiplets and the development of a chiplet ecosystem. Most chiplet-based designs are now produced by a single vendor using proprietary chip-to-chip interconnect technologies for performance and power benefits.

In August 2022, the Universal Chiplet Interconnect Express (UCIe) was established to develop an open specification for die-to-die interconnects, addressing the need for chiplet standards.

In this talk, Professor Sezer will overview emerging chiplet technology, highlighting challenges and opportunities for the semiconductor industry. He will also discuss the UCIe consortium's efforts to develop open specifications for die-to-die interconnects.

Abstract:

Hardware accelerators play a crucial role to accelerate Deep Learning on High Performance Computing systems and data centers providing the computational power needed to process vast amounts of data and train complex models. With the growing demand to run Deep Learning models directly on edge devices -- such as embedded systems, mobile phones, and IoT smart devices, energy-efficient hardware solutions have become increasingly important. This talk explores hardware accelerators across the spectrum, from HPC systems to edge devices, highlighting their role to speed up Deep Learning wokloads by reducing execution times and improving energy efficiency.

Abstract:

Historically, adiabatic logic has been associated with ultra-low-power applications but dismissed for high-performance computing due to its requirement that it should run at a lower rate than the intrinsic RC delay of the technology in order to attain its power savings. However, with the advent of advanced technology nodes such as FinFET, nanosheet and beyond, the paradigm is shifting since the conventional circuit speed is no longer limited by the maximum device speed but rather by power and thermal constraints. This means that adiabatic logic circuits can now attain their power savings even at GHz rates since that will still be lower than the intrinsic RC delay of the advanced node technology. This keynote explores how resonant power extraction and optimized adiabatic logic families such as Positive Feedback Adiabatic Logic (PFAL) can enable energy-efficient yet high-speed computing in such advanced nodes. We also discuss the role of standing-wave oscillators (SWOs) in generating multi-phase sinewave clocks and how optimized transistor design and layout strategies in modern nodes contribute to adiabatic efficiency. Finally, we present simulation results and case studies that demonstrate the feasibility of high-performance, low-power adiabatic circuits for next-generation computing applications.