Technical Session 1A
Monday
July 1
10:00 - 11:20
|
Technical Session 1A: Circuits, Reliability, and Fault-Tolerance
Chair: Jie Gu
An 8-bit 1 MS/s Low-Power SAR ADC with an Enhanced EPC for Implantable Medical Devices
Deepika Kumaradasan, Sougata Kumar Kar, and Santanu Sarkar
(Best Paper Candidate)
Generating Storage-Aware Test Sets Targeting Several Fault Models
Hari Addepalli, Irith Pomeranz, Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, and Srikanth Venkataraman
Sub-Micron Binary HyperPixel Sensor Circuit: In-Pixel Binarization with Variable Thresholding
Md Rahatul Islam Udoy, Md Mazharul Islam, Akhilesh Jaiswal, and Ahmedullah Aziz
Ultra-Small Area, Highly Linear, Modified All Mosfet Digital-To-Analog Converters with Novel Real time Digital Calibration Algorithm
Ekaniyere Oko-Odion, Isaac Bruce, Emmanuel Nti Darko, Michael Sekyere, Kushagra Bhatheja, and Degang Chen
|
|
Technical Session 1B
Monday
July 1
10:00 - 11:20
|
Technical Session 1B: Computer-Aided Design and Verification
Chair: Ujjwal Guin
Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC
Mohamed Naeim, Sudipta Das, Herman Oprins, Geert Van der Plas, Yun Dai, Pinhong Chen, Ct Kao, Dwaipayan Biswas, and Dragomir Milojevic
Automated Deep Neural Network Inference Partitioning for Distributed Embedded Systems
Fabian Kreß, El Mahdi El Annabi, Tim Hotfilter, Julian Höfer, Tanja Harbaum, and Juergen Becker
Thermal Implications in Scaling High-Performance Server 3D Chiplet-based 2.5D SoC from FinFET to Nanosheet
Yukai Chen, Venkateswarlu Sankatali, Subrat Mishra, Julien Ryckaert, James Myers, and Dwaipayan Biswas
Energy-Aware Incremental OTA Update for Flash-based Batteryless IoT Devices
Wei Wei, Jishnu Banerjee, Sahidul Islam, Chen Pan, and Mimi Xie
|
|
Technical Session 2A
Monday
July 1
11:30 - 12:50
|
Technical Session 2A: Digital Circuits and FPGA-based Designs I
Chair: Ahmed Aziz
Design of Multiplier Circuit Based on Signed-Digit Hybrid Stochastic Computing
Yinjie Song, Hongge Li, Xinyu Zhu, and Yuhao Chen
(Best Paper Candidate)
Energy-Efficient Design of Approximate VVC Interpolation Filters Units
Rafael da Silva, Mateus Grellert, and Ricardo Reis
(Best Paper Candidate)
Adaptive and Offloaded CNNs for IoT-Edge FPGAs
Guilherme Korol and Antonio Carlos Schneider Beck Filho
(Best Paper Candidate)
HIERA: High-Quality and High-Throughput Dehazing Hardware Accelerator with Reconfigurable Computing Unit
Junhao Zhang, Dongqi Fan, and Liang Chang
|
|
Technical Session 2B
Monday
July 1
11:30 - 12:50
|
Technical Session 2B: Emerging and Post-CMOS Technologies I
Chair: Ramtin Zand
Area-efficient Digital Design using RRAM-CMOS Standardcells
Markus Fritscher, Max Uhlmann, Philip Ostrovskyy, Daniel Reiser, Junchao Chen, Schubert Andreas, Carsten Schulze, Gerhard Kahmen, Dietmar Fey, Marc Reichenbach, Milos Krstic, and Christian Wenger
(Best Paper Candidate)
DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing
Muhammad Awais, Hassan Ghasemzadeh Mohammadi, and Marco Platzner
(Best Paper Candidate)
A High-accuracy Time-efficient Error Metric Model for Approximate Computing Circuits
Shouji Chen, Ke Chen, Ziying Cui, and Weiqiang Liu
Random Microfluidic Chip Design with Diagonal Channels Using K-Means Clustering for Fluid Dilutions
Ankita Agrawal and Sudip Roy
|
|
Technical Session 3A
Tuesday
July 2
10:00 - 11:40
|
Technical Session 3A: VLSI for Applied and Future Computing I
Chair: Ramtin Zand
Most Significant Digit First Multiply-and-Accumulate Unit for Neural Networks
Sahar Moradi Cherati, Mohsen Barzegar, and Leonel Sousa
(Best Paper Candidate)
Exploring a Hybrid SRAM-RRAM Computing-In-Memory Architecture for DNNs Model Inference
Yu-Guang Chen, Zhi-Wei Liu, and Ying-Jing Tsai
(Best Paper Candidate)
Accelerating Large Language Model Training with In-Package Optical Links for Scale-Out Systems
Aakash Patel, Dwaipayan Biswas, Joyjit Kundu, Yoojin Ban, Nicolas Pantano, Arindam Mallik, Julien Ryckaert, and James Myers
BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM
Xiaojie Li, Mingyu Wang, Yangzhan Mai, Yicong Zhang, Baiqing Zhong, and Zhiyi Yu
SHIFFT: A Scalable Hybrid In-Memory Computing FFT Accelerator
Pragnya Sudershan Nalla, Zhenyu Wang, Sapan Agarwal, T. Patrick Xiao, Christopher H. Bennett, Matthew J. Marinella, Jae-sun Seo, and Yu Cao
|
|
Technical Session 4A
Tuesday
July 2
1:25 - 2:45
|
Technical Session 4A: System Design and Security I
Chair: Amit Degada
RFET-based Dynamic Differential Logic Cells Against Power Side-Channel Attacks
Nima Kavand, Armin Darjani, Garvit Chhabra, and Akash Kumar
Enhancing Graph Execution for Performance and Energy Efficiency on NUMA Machines
Hiago Mayk Gomes de Araújo Rocha, Marcelo Koji Moori, Arthur Francisco Lorenzon, and Antonio Carlos Schneider Beck
Towards Quantum-Resistant Security: Pre-Silicon Power Side-Channel Leakage Analysis of CRYSTALS-Kyber
Nashmin Alam, Tao Zhang, and Farimah Farahmandi
Efficient Federated Learning through Distributed Model Pruning
Mohammed Alawad
|
|
Technical Session 5A
Tuesday
July 2
2:55 - 4:15
|
Technical Session 5A: System Design and Security II
Chair: Tauhidur Rahman
DAW-DMR: Divergence-Aware Warped DMR with Full Error Detection for GPGPUs
Yukun Wei, Mingyu Wang, Haiqiu Huang, Wangguang Wang, and Zhiyi Yu
Embedding Power Signature Generation into Low Dropout Voltage Regulators for Enhancing IoT Security
Ashish Mahanta and Haibo Wang
A Fine-Grained Dynamic Partitioning Against Cache-Based Timing Attacks via Cache Locking
Nicolas Gaudin, Pascal Cotret, Guy Gogniat, and Vianney Lapotre
Defending the Citadel: Fault Injection Attacks against Dynamic Information Flow Tracking and Related Countermeasures
William Pensec, Francesco Regazzoni, Vianney Lapotre, and Guy Gogniat
|
|
Technical Session 5B
Tuesday
July 2
2:55 - 4:15
|
Technical Session 5B: VLSI for Applied and Future Computing II
Chair: Mohammed Alawad
Energy-Efficient and Low-Latency Computation of Transcendental Functions in a Precision-Tunable PIM Architecture
Gian Singh, Ayushi Dube, and Sarma Vrudhula
In-Sensor Motion Recognition with Memristive System and Light Sensing Surfaces
Hritom Das, Imran Fahad, Snb Tushar, Sk Hasibul Alam, Graham Buchanan, Dan Scott, Garrett S. Rose, and Sai Swaminathan
SNN-ANN Hybrid Networks for Embedded Multimodal Monocular Depth Estimation
Sadia Anjum Tumpa, Anusha Devulapally, Matthew Brehove, Espoir Kyubwa, and Vijaykrishnan Narayanan
DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-Defined SIMD
Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, and Francky Catthoor
|
|
Technical Session 6A
Wednesday
July 3
12:45 - 2:05
|
Technical Session 6A: Digital Circuits and FPGA-based Designs II
Chair: Peipei Zhou
Optimizing LU Decomposition with RISC-V Based Hardware Acceleration
Bindu Bhargavi Mekala, Sai Sri Harshith Grandhala, Sri Parameswaran, and Soumya J.
Unfolded SiBM BCH Decoders for High-Throughput Low-Latency Applications
Xu Wang, Christoffer Fougstedt, Lars Svensson, and Per Larsson-Edefors
Boosting Multiple Multipliers Packing on FPGA DSP Blocks via Truncation and Compensation-based Approximation
Behnam Ghavami, Madi Sajadi, Lesley Shannon, and Steve Wilton
High Energy Efficiency Radix-4 Booth Multiplier with Zero Encoding Skipping Mechanism
Xinyu Zhu, Hongge Li, Yinjie Song, Yuhao Chen, and Xiaoyu Guo
|
|
Technical Session 6B
Wednesday
July 3
12:45 - 2:05
|
Technical Session 6B: VLSI for Applied and Future Computing III
Chair: Catherine Schuman
Dynamic Exit Selection for Comprehensive and Energy Efficient Gait-Based User Authentication on IoT Devices
Pavlos Zouridakis and Sai Manoj P. D.
Compressed Latent Replays for Lightweight Continual Learning on Spiking Neural Networks
Alberto Dequino, Alessio Carpegna, Davide Nadalini, Alessandro Savino, Luca Benini, Stefano Di Carlo, and Francesco Conti
Machine Learning Based Decoding of Heavy Hexagonal QECC for Asymmetric Quantum Noise
Debasmita Bhoumik, Ritajit Majumdar, Dhiraj Madan, and Susmita Sur-Kolay
HO-FPIA: High-Order Field-Programmable Ising Arrays with In-Memory Computing
Tinish Bhattacharya, George Higgins Hutchinson, Giacomo Pedretti, and Dmitri Strukov
|
|
Technical Session 7A
Wednesday
July 3
2:15 - 3:35
|
Technical Session 7A: Emerging and Post-CMOS Technologies II
Chair: Hritom Das
Towards Thermally Reliable Photonic Links for Multicore Processors
Yuxiang Fu, Xuanqi Chen, Jiaxu Zhang, Shixi Chen, and Jiang Xu
An Efficient and Scalable Clocking Assignment Algorithm for Multi-Threaded Multi-Phase Single Flux Quantum Circuits
Robert S. Aviles, Xi Li, Lei Lu, Zhaorui Ni, and Peter A. Beerel
Technology Mapping for Cryogenic CMOS Circuits
Benjamin Hien, Marcel Walter, Victor M. van Santen, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh S. Chauhan, Hussam Amrouch, and Robert Wille
Automatic Validation and Design of Microfluidic Devices Following the ISO 22916 Standard
Philipp Ebner and Robert Wille
|
|