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Program Schedule
You can click on the program schedule to learn more about any specific session.
TIME |
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MONDAY JULY 4th 2022 |
8:00
- 8:30 |
|
Registration (Main Entrance - Arion Cafe) |
8:30 - 9:00 |
|
Opening Plenary Session - Welcome presentations (Pantheon
Ballroom) |
9:00 - 10:00 |
|
Keynote I (Pantheon Ballroom)
Moderated by: J. Becker and T. Theocharides |
Neuromorphic Intelligence
Giacomo Indiveri |
10:00-10:30 |
|
COFFEE BREAK (Arion Cafe) |
10:30-11:45 |
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Session 1 (Pantheon
Ballroom) |
|
Special Session 1 (Adonis
Room) |
Hardware
Acceleration |
Secure and Dependable
Cyberphysical Systems I |
11:45-13:00 |
|
Session 2
(Pantheon Ballroom) |
|
Special Session 2 (Adonis Room) |
Reliability,
Fault-Tolerance, and Fault Diagnosis |
Secure and Dependable
Cyberphysical Systems II |
13:00-14:00 |
|
LUNCH BREAK |
14:00-15:00 |
|
PANEL - ISVLSI - The past (20
years) the present and the future! (Pantheon Ballroom)
Moderated by: V. Narayanan |
15:00-15:45 |
|
Plenary Talk I - In Memory
Processing (Pantheon Ballroom)
Onur Mutlu
Moderated by: M. Shafique |
15:45-16:00 |
|
COFFEE BREAK (Arion Cafe) |
16:00 - 17:15 |
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Session 3 (Pantheon
Ballroom) |
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Special Session 3 (Adonis
Room) |
Simulation
and Design Automation |
In Memory Processing I |
17:15-19:00 |
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Session 4
(Pantheon Ballroom) |
|
Special Session 4 (Adonis Room) |
Emerging
and Post-CMOS Technologies 1 |
In Memory Processing II |
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TIME |
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Tuesday July 5th 2022 |
8:00-8:30 |
|
Registration (Main
Entrance - Arion Cafe) |
8:30-9:30 |
|
Keynote II (Pantheon Ballroom)
Moderated by: M. Maniatakos |
Recent Advances in
Ferroelectric-based Logic and Memory Architectures
Vijay Narayanan |
9:30-10:45 |
|
Session 5 (Pantheon
Ballroom) |
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Special Session 5 (Adonis
Room) |
Test
and Verification |
Secured Neurmorphic
Computing I |
10:45-11:05 |
|
Student Poster Pitch
(Pantheon Ballroom) |
11:05 - 11:45 |
|
COFFEE BREAK - Student Posters (Arion Cafe) |
11:45-13:00 |
|
Session 6 (Pantheon
Ballroom) |
|
Special Session 6 (Adonis
Room) |
High
Speed Computing - Accelerators and Asynchronous Circuits |
Secured Neurmorphic
Computing II |
13:00-14:00 |
|
LUNCH BREAK |
14:00-14:45 |
|
Embedded Tutorial - VLSI Design
Optimization (Pantheon Ballroom)
Ricardo Reis
Moderated by: M. Shafique |
14:45- 15:45 |
|
Poster Session (Pantheon Ballroom) |
15:45-16:30 |
COFFEE BREAK + Posters (Arion
Cafe) |
16:30-17:45 |
|
Session 7
(Pantheon Ballroom) |
|
Session 8
(Adonis Room) |
Emerging and Post-CMOS Technologies 2 |
Hardware Security 1 |
19:00 - 23:00 |
SOCIAL EVENT - DINNER AND BEACH PARTY |
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TIME |
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Wednesday July 6th 2022 |
8:30 - 9:00 |
|
Registration
(Main Entrance - Arion Cafe) |
9:00- 10:00 |
|
Keynote III (Pantheon Ballroom)
Moderated by: M. K. Michael |
TinyML for tiny embedded
systems
Elisabetta Farella |
10:00 -
10:30 |
|
COFFEE
BREAK (Arion Cafe) |
10:30-11:45 |
|
Session 9 (Pantheon Ballroom) |
|
Special Session 7 (Adonis Room) |
Future
Computing and Learning Techniques |
Approximate Computing for
ML |
11:45-13:00 |
|
Session 10 (Pantheon Ballroom) |
|
Special Session 8 (Adonis Room) |
Hardware Security 2 |
Towards Efficient Testing
of AI Accelerators |
13:00-14:00 |
|
LUNCH
BREAK |
14:00-15:30 |
|
Session 11 (Pantheon Ballroom) |
|
Special Session 10 (Adonis Room) |
Delay-
Aware and Energy-Aware Design |
EU Multi-Partner Projects |
15:30-
15:50 |
|
Research
Demo Pitch (Pantheon Ballroom) |
15:50
-16:15 |
|
COFFEE BREAK + Research Demos (Arion Cafe) |
16:15
- 17:30 |
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Session 12 (Pantheon Ballroom) |
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Special Session 9 (Adonis Room) |
Circuits
for Networking and Communication |
Embedded ML |
17:30 - 17:45 |
|
Closing
Session (Pantheon Ballroom) |
Research Demo Awards/Student Poster Awards |
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Regular Session Details
Time |
Paper Title |
Authors |
MONDAY JULY 4th 2022 |
Session 1: Hardware Acceleration |
Session Chair: Maksim Jenihhin, Tallinn University
of Technology, Estonia |
10:30 |
HAJPAQUE: Hardware Accelerator for JSON Parsing, Querying and
Schema Validation |
Samiksha Agarwal and Smruti Sarangi (IIT Delhi, India) |
10:55 |
Design and Evaluation of On-Chip DCT Accelerators Based on Novel
Approximate Reverse Carry Propagate Adders |
Shalini Singh (International Institute of Information Technology
Bangalore, India); Pavan Kumar Pothula (International Institute of
Information Technology, Bangalore, India); Madhav Rao (International
Institute of Information Technology - Bangalore, India) |
11:20 |
Spiker: FPGA-Optimized Hardware Accelerator for Spiking Neural
Networks |
Alessio Carpegna, Stefano Di Carlo and Alessandro Savino
(Politecnico di Torino, Italy) |
|
Session 2: Reliability, Fault-Tolerance, and Fault
Diagnosis |
Session Chair: Stefano Di Carlo, Politecnico di
Torino, Italy |
11:45 |
A Methodology for Identifying Critical Sequential Circuits With
Graph Convolutional Networks |
Li Lu, Markus Ulbricht, Milos Krstic and Junchao Chen (IHP,
Germany) |
12:10 |
Microarchitectural Reliability Evaluation of a Block Scheduling
Controller in GPUs |
Josie Esteban Rodriguez Condia, Riccardo Faggiano and Matteo
Sonza Reorda (Politecnico di Torino, Italy) |
12:35 |
High-Level Fault Diagnosis in RISC Processors With
Implementation-Independent Functional Test |
Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik and Raimund
Ubar (Tallinn University of Technology, Estonia) |
|
Session 3: Simulation and Design Automation |
Session Chair: Angeliki Kritikakou, Universita de
Rennes 1, Inria, IRISA, CNRS, France |
16:00 |
An Exploration Platform for Microcoded RISC-V Cores Leveraging
the One Instruction Set Computer Principle |
Lucas Klemmer, Johannes Kepler University Linz, Austria
Daniel Grosse, Johannes Kepler University Linz, Austria |
16:25 |
Soft Tiles: Capturing Physical Implementation Flexibility for
Tightly-Coupled Parallel Processing Clusters |
Gianna Paulin, ETH Zurich, Switzerland
Matheus Cavalcante, ETH Zurich, Switzerland
Paul Scheffler, ETH Zurich, Switzerland
Luca Bertaccini, ETH Zurich, Switzerland
Yichao Zhang, ETH Zurich, Switzerland
Frank Gurkaynak, ETH Zurich, Switzerland
Luca Benini, ETH Zurich, Switzerland |
16:50 |
MIDAS: Mutual Information Driven Approximate Synthesis |
Sina Boroumand, Imperial College London, United Kingdom (Great
Britain)
Christos-Savvas Bouganis , Imperial College London, United Kingdom (Great
Britain)
George Constantinides, Imperial College UK, United Kingdom (Great
Britain) |
|
Session 4: Emerging and Post-CMOS Technologies 1 |
Session Chair: Chrysostomos Nicopoulos, University
of Cyprus, Cyprus |
17:15 |
Processing-In-Memory With Temporal Encoding |
Mohammad Nazmus Sakib, Rahul Sreekumar, Xinyuan Zhu, Tommy Tracy
II and Mircea Stan (University of Virginia, USA) |
17:40 |
Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined
Superconductive Logic |
Xi Li (University of Southern California, USA); Min Pan and Tong
Liu (Synopsys Inc., USA); Peter A. Beerel (University of Southern California,
USA) |
18:05 |
Variation-Aware Design Space Exploration of Mott Memristor-Based
Neuristors |
Shamiul Alam and Md Mazharul Islam (University of
Tennessee Knoxville, USA); Akhilesh Jaiswal (University of Southern
California, USA); Nathaniel Cady (College of Nanoscale Science and
Engineering, SUNY Polytechnic Institute, USA); Garrett S.
Rose (University of Tennessee, Knoxville, USA); Ahmedullah
Aziz (University of Tennessee Knoxville, USA) |
18:30 |
A Study of STTRAM-Based Page Walker Caches for Energy-Efficient
Address Translation |
Kyle Kuan and Tosiron Adegbija (University of Arizona, USA) |
|
TUESDAY JULY 5th 2022 |
Session 5: Test and Verification |
Session Chair: Stelios Neophytou, University of
Nicosia, Cyprus |
09:30 |
Deriving FSM-Based Tests Using a, b-Faults for Logic Circuits |
Andrey Laputenko (Tomsk State University, Russia); Nina
Yevtushenko (Ivannikov Institute for System Programming of the Russian
Academy of Sciences, Russia); Valentina Andreeva and Anzhela Matrosova (Tomsk
State University, Russia) |
09:55 |
Optimization of BDD-Based Approximation Error Metrics
Calculations |
Vojtech Mrazek, Brno University of Technology, Czech Republic |
10:20 |
Polynomial Formal Verification of Approximate Functions |
Martha Schnieber, University of Bremen, Germany
Saman Froehlich, University of Bremen, Germany
Rolf Drechsler, University of Bremen/DFKI, Germany |
|
Session 6: High Speed Computing - Accelerators and
Asynchronous Circuits |
Session Chair: Georgios Keramidas, Aristotle
University of Thessaloniki, Greece |
11:45 |
RecLight: A Recurrent Neural Network Accelerator With Integrated
Silicon Photonics |
Febin P Sunny (Colorado State University, USA); Mahdi Nikdast
(Colorado State University Fort Collins, USA); Sudeep Pasricha (Colorado
State University, USA) |
12:10 |
Automated Mapping of Asynchronous Circuits on FPGA Under Timing
Constraints |
Gang Mao, Alex Yakovlev, Fei Xia and Rishad
Shafik (Newcastle University, United Kingdom (Great
Britain)); Shengqi Yu (Newcastle University & Microsystem
Group, China) |
12:35 |
An Efficient Accelerator of Deformable 3D Convolutional Network
for Video Super-Resolution |
Siyu Zhang, Wendong Mao and Zhongfeng
Wang (Nanjing University, China) |
|
Session 7: Emerging and Post-CMOS Technologies 2 |
Session Chair: Georgios Ellinas, University of
Cyprus, Cyprus |
16:30 |
Adaptable Multi-Level Voltage to Binary Converter Using
Ferroelectric FETs |
Sanjay Das and Arun Govindankutty (North Dakota State
University, USA); Shan Deng (Rochester Institute of Technology, USA); Kai Ni
(RIT, USA); Sumitha George (NDSU, ECE & NDSU, USA) |
16:55 |
Energy-Efficient High-Performance Photonic Backplane Network for
Rack-Scale Computing Systems |
Jun Feng, Shixi Chen, Jiaxu Zhang and Yuxiang Fu (Hong Kong
University of Science and Technology, Hong Kong); Jiang Xu (Hong Kong
University of Science and Technology (Guangzhou), China) |
17:20 |
Pruning Coherent Integrated Photonic Neural Networks Using the
Lottery Ticket Hypothesis |
Sanmitra Banerjee (Duke University, USA); Mahdi Nikdast
(Colorado State University Fort Collins, USA); Sudeep Pasricha (Colorado
State University, USA); Krishnendu Chakrabarty (Duke University, USA) |
|
Session 8: Hardware Security 1 |
Session Chair: Ricardo Reis, Universidade Federal
do Rio Grande do Sul, Brazil |
16:30 |
LDTFI: Layout-Aware Timing Fault-Injection Attack Assessment
Against Differential Fault Analysis |
Amit Mazumder Shuvo, Nitin Pundir, Jungmin Park, Farimah
Farahmandi and Mark M. Tehranipoor (University of Florida, USA) |
16:55 |
ISPLock: A
Hybrid Internal State Locking Method Using Polymorphic Gates |
Nikhil Saxena, University of Cincinnati, USA
Ranga Vemuri, University of Cincinnati, USA |
17:20 |
On Protecting IJTAG From Data Sniffing and Alteration Attacks |
Anjum Riaz and Gaurav Kumar (Indian Institute of Technology
Jammu, India); Jaynarayan Tudu (Indian Institute of Technology Tirupati,
India); Satyadev Ahlawat (Indian Institute of Technology Jammu, India) |
|
WEDNESDAY JULY 6th 2022 |
Session 9: Future Computing and Learning
Techniques |
Session Chair: Nektarios Tsoutsos, University of
Delaware, USA |
10:30 |
TNN7: A Custom Macro Suite for Implementing Highly Optimized
Designs of Neuromorphic TNNs |
Harideep Nair, Prabhu Vellaisamy, Santha
Bhasuthkar and John P. Shen (Carnegie Mellon University, USA) |
10:55 |
Performance Evaluation of Video Analytics Workloads on Emerging
Processing-In-Memory Architectures |
Nagadastagiri R Challapalle (The Pennsylvania State
University, USA); Vijaykrishnan Narayanan (Pennsylvania State
University, USA) |
11:20 |
Power Management for Chiplet-Based Multicore Systems Using Deep
Reinforcement Learning |
Xiao Li, Lin Chen, Shixi Chen, Fan Jiang and Chengeng Li (Hong
Kong University of Science and Technology, Hong Kong); Jiang Xu (Hong Kong
University of Science and Technology (Guangzhou); Guangzhou HKUST For Ying
Tung Research Institute, China) |
|
Session 10: Hardware Security 2 |
Session Chair: Vijay Narayanan, Penn State
University, USA |
11:45 |
ZK-Sherlock: Exposing Hardware Trojans in Zero-Knowledge |
Dimitris Mouris, Charles Gouert and Nektarios Tsoutsos
(University of Delaware, USA) |
12:10 |
LOKI: A Hardware Trojan Affecting Multiple Components of an SoC |
Manju R (Indian Institute of Technology Guwahati, India);
Abhijit Das (INRIA, France); John Jose (Indian Institute of Technology
Guwahati, India) |
12:35 |
Enhancing Security of Memristor Computing System Through Secure
Weight Mapping |
Minhui Zou (Technion - Israel Institute of Technology,
Israel); Junlong Zhou (Nanjing University of Science and
Technology, China); Xiaotong Cui (Chongqing University of Posts and
Telecommunications, China); Wei Wang and Shahar
Kvatinksy (Technion - Israel Institute of Technology, Israel) |
|
Session 11: Delay- Aware and Energy-Aware Design |
Session Chair: Virendra Singh, Indian Institute of
Technology Bombay, India |
14:00 |
Delay-Aware Evolutionary Optimization of Digital Circuits |
Jitka Kocnova and Zdenek Vasicek (Brno University of Technology,
Czech Republic) |
14:25 |
CmpctArch: A Generic Low Power Architecture for Compact Data
Structures in Energy Harvesting Devices |
Priyanka Singla (Indian Institute of Technology, Delhi, India);
Smruti Sarangi (IIT Delhi, India) |
14:50 |
LeapConv: An Energy-Efficient Streaming Convolution Engine With
Reconfigurable Stride |
Dionysios Filippas (Democritus University of Thrace, Greece);
Chrysostomos Nicopoulos (University of Cyprus, Cyprus); Giorgos
Dimitrakopoulos (Democritus University of Thrace, Greece) |
|
Session 12: Circuits for Networking and
Communication |
Session Chair: Muhammad Shafique, NYU Abu Dhabi,
UAE |
16:15 |
High-Throughput VLSI Architecture for LDPC Decoder Based on
Low-Latency Decoding Technique for Wireless Communication Systems |
Suravi Kumari (Qualcomm Incorporation, India); Rahul Shrestha
(Indian Institute of Technology (IIT) Mandi, India) |
16:40 |
An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking |
Lei Yang, Jing Tian, Zhongfeng Wang and Bo Wu (Nanjing
University, China); Hao Ren (Huawei Technologies Company, China) |
17:05 |
A Random Linear Network Coding Platform MPSoC Designed in 22nm
FDSOI |
Mattis Hasler and Sebastian Haas (Barkhausen Institut, Germany);
Robert Wittig, Stefan Scholze, Andreas Dixius and Sebastian Hoppner (TU
Dresden, Germany); Gerhard Fettweis (Barkhausen Institut, Germany); Christian
Mayr (TU Dresden, Germany) |
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Special Session Details
MONDAY JULY 4th 2022 |
Special Session 1: Secure and Dependable
Cyberphysical Systems I |
Session Chair: Deepak Puthal, Khalifa University,
UAE |
Time |
Title |
Authors |
10:30 |
Improving GPU Throughput Through Parallel Execution Using Tensor
Cores and CUDA Cores |
Khoa L. D. Ho (University of North Texas (UNT), USA); Hui Zhao
(University of North Texas, USA); Adwait Jog (William and Mary University,
USA); Saraju P Mohanty (University of North Texas, USA) |
10:55 |
CosMos: Building A Network Reliability Cost Modeling System for
Customer SLA |
Manasa Leela Gummadavelly and Haymanot Gebre-Amlak (University
of Missouri-Kansas City, USA); Baek-Young Choi (University of Missouri -
Kansas City, USA); Henry Zhu (University of Missouri Kansas City (UMKC),
USA); Sejun Song (University of Missouri Kansas City, USA) |
11:20 |
Adiabatic Logic-Based STT-MRAM Design for IoT |
Wu Yang and Amit Degada (University of Tennessee, Knoxville, TN,
USA); Himanshu Thapliyal (University of Tennessee, USA) |
Special Session 2: Secure and Dependable
Cyberphysical Systems II |
Session Chair: Deepak Puthal, Khalifa University,
UAE |
Time |
Title |
Authors |
11:45 |
Robust Perception Architecture Design for Automotive
Cyber-Physical Systems |
Joydeep Dey, Colorado State University, USA
Sudeep Pasricha, Colorado State University, USA |
12:10 |
Secure and Scalable Collaborative Edge Computing Using Decision
Tree |
Deepak Puthal (Khalifa University, United Arab Emirates);
Ernesto Damiani (Khalida University - EBTIC, United Arab Emirates); Saraju P
Mohanty (University of North Texas, USA) |
12:35 |
Predicting GPU Performance and System Parameter Configuration
Using Machine Learning |
Zhuren Liu (UNT, USA); Trevor Exley (University of North Texas,
USA); Austin Meek and Rachel Yang (UNT, USA); Hui Zhao (University of North
Texas, USA); Mark Albert (UNT, USA) |
Special Session 3: In Memory Processing I |
Session Chair: Juan Gomez Luna, ETH Zurich,
Switzerland |
Time |
Title |
Authors |
16:00 |
The Road to Widely Deploying Processing-In-Memory: Challenges
and Opportunities |
Saugata Ghose (University of Illinois Urbana-Champaign, USA) |
16:25 |
Methodologies, Workloads, and Tools for Processing-In-Memory:
Enabling the Adoption of Data-Centric Architectures |
Geraldo Francisco De Oliveira Junior (ETH Zurich, Switzerland);
Juan Gomez Luna (ETH, Switzerland); Saugata Ghose (University of Illinois
Urbana-Champaign, USA); Onur Mutlu (ETH Zurich, Switzerland) |
16:50 |
PiDRAM: An FPGA-Based Framework for End-To-End Evaluation of
Processing-In-DRAM Techniques |
Ataberk Olgun (ETH Zurich, Switzerland); Juan Gomez Luna (ETH,
Switzerland); Konstantinos Kanellopoulos and Behzad Salami (ETH Zurich,
Switzerland); Hasan Hassan (ETH Zurich); Oguz Ergin (TOBB University of
Economics and Technology, Turkey); Onur Mutlu (ETH Zurich, Switzerland) |
Special Session 4: In Memory Processing II |
Session Chair: Juan Gomez Luna, ETH Zurich,
Switzerland |
Time |
Title |
Authors |
17:15 |
Heterogeneous Data-Centric Architectures for Modern
Data-Intensive Applications: Case Studies in Machine Learning and Databases |
Geraldo Francisco De Oliveira Junior (ETH Zurich, Switzerland);
Saugata Ghose (University of Illinois Urbana-Champaign, USA); Juan Gomez Luna
(ETH, Switzerland); Onur Mutlu (ETH Zurich, Switzerland) |
17:40 |
Exploiting Near-Data Processing to Accelerate Time Series
Analysis |
Ivan Fernandez (University of Malaga & ETH Zurich, Spain);
Ricardo Quislant (University of Malaga, Spain); Christina Giannoula (National
Technical University of Athens & ETH Zurich, Greece); Mohammed Alser and
Juan Gomez Luna (ETH, Switzerland); Eladio D Gutierrez and Oscar Plata
(University of Malaga, Spain); Onur Mutlu (ETH Zurich, Switzerland) |
18:05 |
GenStore: In-Storage Filtering of Genomic Data for
High-Performance and Energy-Efficient Genome Analysis |
Nika Mansouri Ghiasi, Jisung Park, Harun Mustafa, Jeremie Kim,
Ataberk Olgun and Arvid Gollwitzer (ETH Zurich, Switzerland); Damla Senol
Cali (Bionano Genomics, USA); Can Firtina, Haiyu Mao and Nour Almadhoun
Alserr (ETH Zurich, Switzerland); Rachata Ausavarungnirun (KMUTNB, Thailand);
Nandita Vijaykumar (University of Toronto, Canada); Mohammed Alser and Onur
Mutlu (ETH Zurich, Switzerland) |
18:30 |
SparseP: Efficient Sparse Matrix Vector Multiplication on Real
Processing-In-Memory Architectures |
Christina Giannoula (National Technical University of Athens
& ETH Zurich, Greece); Ivan Fernandez (University of Malaga & ETH
Zurich, Spain); Juan Gomez-Luna (University of Cordoba, Spain); Nectarios
Koziris and Georgios Goumas (National Technical University of Athens,
Greece); Onur Mutlu (ETH Zurich, Switzerland) |
18:55 |
Machine Learning Training on a Real Processing-In-Memory System |
Juan Gomez Luna and Yuxin Guo (ETH, Switzerland); Sylvan
Brocard, Julien Legriel and Remy Cimadomo (UPMEM, France); Geraldo Oliveira
and Gagandeep Singh (ETH, Switzerland); Onur Mutlu (ETH Zurich, Switzerland) |
TUESDAY JULY 5th 2022 |
Special Session 5: Secured Neurmorphic Computing I |
Session Chair: Minhui Zhu, Technion - Israel
Institute of Technology, Israel |
Time |
Title |
Authors |
09:30 |
WESCO: Weight-Encoded Reliability and Security Co-Design for
In-Memory Computing Systems |
Jiangwei Zhang, Chong Wang, Yi Cai and Zhenhua Zhu (Tsinghua
University, China); Donald Kline Jr. (Intel Corp., USA); Huazhong Yang and Yu
Wang (Tsinghua University, China) |
09:55 |
A Method for Reverse Engineering Neural Network Parameters From
Compute-In-Memory Accelerators |
James L Read, Wantong Li and Shimeng Yu (Georgia Institute of
Technology, USA) |
10:20 |
SCRAMBLE: A Secure and Configurable, Memristor-Based
Neuromorphic Hardware Leveraging 3D Architecture |
Nikhil Rangarajan (New York University Abu Dhabi, United Arab
Emirates); Satwik Patnaik (Texas A&M University, USA); Mohammed Nabeel
and Mohammed Ashraf (New York University Abu Dhabi, United Arab Emirates);
Shubham Rai (TU Dresden, Germany); Gopal Raut (IIT Indore, India); Heba Abu
Nahla (Khalifa University); Baker Mohammad (Khalifa University, United Arab
Emirates); Santosh Kumar Vishvakarma (IIT, Indore, India); Akash Kumar (TU
Dresden); Johann Knechtel and Ozgur Sinanoglu (New York University Abu Dhabi,
United Arab Emirates) |
Special Session 6: Secured Neurmorphic Computing
II |
Session Chair: Minhui Zhu, Technion - Israel
Institute of Technology, Israel |
Time |
Title |
Authors |
11:45 |
Security as an Important Ingredient in Neuromorphic Engineering |
Farhad Amirali Merchant (RWTH Aachen University, Germany) |
12:10 |
A DNN Protection Solution for PIM Accelerators With Model
Compression |
Lei Zhao, Youtao Zhang and Jun Yang (University of Pittsburgh,
USA) |
WEDNESDAY JULY 6th 2022 |
Special Session 7: Approximate Computing for ML |
Session Chair: Angeliki Kritikakou, Universita de
Rennes 1, Inria, IRISA, CNRS, France |
Time |
Title |
Authors |
10:30 |
Exploiting Approximate Computing for Efficient and Reliable
Convolutional Neural Networks |
Alberto Bosio (Ecole Centrale de Lyon, Institute of
Nanotechnology, France); Bastien Deveautour (CPE Lyon, INL, France); Ian
O'Connor (Lyon Institute of NanoTechnology & Ecole Centrale de Lyon,
France) |
10:55 |
Evaluating the Impact of Mixed-Precision on Fault Propagation
for Deep Neural Networks on GPUs |
Fernando F. dos Santos (Univ of Rennes INRIA, France); Paolo
Rech (University of Trento, Italy); Angeliki Kritikakou (Univ Rennes, Inria,
IRISA, CNRS, France); Olivier Sentieys (INRIA, France) |
11:20 |
Energy-aware Adaptive Approximate Computing for Deep Learning
Applications |
Nima TaheriNejad and Salar Shakibhamedan, TU Wien, Vienna,
Austria |
Special Session 8: Towards Efficient Testing of AI
Accelerators |
Session Chair: Chenmo Yang, University of
Delaware, USA |
Time |
Title |
Authors |
11:45 |
Fault Resilience of DNN Accelerators for Compressed Sensor
Inputs |
Ayush Arunachalam and Shamik Kundu (University of Texas at
Dallas, USA); Arnab Raha and Suvadeep Banerjee (Intel Corporation, USA);
Kanad Basu (University of Texas at Dallas, USA) |
12:10 |
Probabilistic Fault Grading for AI Accelerators Using Neural
Twins |
Arjun Chaudhuri, Jonti Talukdar and Krishnendu Chakrabarty (Duke
University, USA) |
12:35 |
Towards Yield Improvement for AI Accelerators: Analysis and
Exploration |
Mohammad Walid Charrwi (City College of New York, USA); Huy Phan
and Bo Yuan (Rutgers University, USA); Samah Saeed (The City College of New
York, CUNY, USA) |
13:00 |
Exploring Image Selection for Self-Testing in Neural Network
Accelerators |
Fanruo Meng (University of Delaware, USA); Chengmo Yang
(University of Delaware, USA, USA) |
Special Session 9: Embedded Machine Learning |
Session Chair: Umamaheswara Rao Tida, North Dakota
State University, USA |
Time |
Title |
Authors |
16:15 |
Towards Independent
On-Device Artificial Intelligence |
Yawen Wu, Jingtong Hu, University of Pittsburgh, USA |
16:40 |
Hardware-aware Automated
Architecture Search for Brain-inspired Hyperdimensional Computing |
Junhuan Yang, Lei Yang, University of New Mexico, USA
Venkat Kalyan Reddy Yasa, Yi Sheng, Weiwen Jiang, George Mason University,
USA
Dayane Reis, University of South Florida, USA
Xun Jiao, Villanova University, USA |
17:05 |
Hardware/Software Co-Exploration for Graph Neural Architectures
on FPGAs |
Qing Lu, Meng Jiang, Yiyu Shi,
University of Notre Dame, USA
Weiwen Jiang, George Mason
University, USA
Jingtong Hu, University of Pittsburgh, USA |
Special Session 10: Multipartner Projects |
Session Chair: Georgios Keramidas, Aristotle
University of Thessaloniki |
Time |
Title |
Authors |
14:00 |
A Novel Marketplace Perspective PromotingCustomized Low Energy
Computing and IoT: The SMART4ALL Approach |
Evanthia Faliagka, University of Peloponnese, Greece
Christos Panagiotou, AVN Innovative Technology Solutions, Cyprus
Christos Antonopoulos, University of Peloponnese, Greece
Georgios Keramidas, Aristotle University of Thessaloniki, Greece
Nikolaos Voros, University of Peloponnese, Greece |
14:25 |
Safety by Construction: Pattern-Based Application |
Tobias Dorr, Karlsruhe Institute of Technology (KIT),
Germany
Florian Schade, Karlsruhe Institute of Technology (KIT), Germany
Leonard Masing, Karlsruhe Institute of Technology (KIT), Germany
Jurgen Becker, Karlsruhe Institute of Technology (KIT), Germany
Georgios Keramidas, Aristotle University of Thessaloniki, Greece
Christos P. Antonopoulos, University of Peloponnese, Greece
Michail Mavropoulos, University of Peloponnese, Greece
Vasilios Kelefouras, University of Peloponnese, Greece
Nikolaos Voros, University of Peloponnese, Greece |
14:50 |
Data Movement Reduction for DNN Accelerators: Enabling Dynamic
Quantization Through an eFPGA. |
Tim Hotfilter, Karlsruhe Institute of Technology (KIT),
Germany
Fabian Kres, Karlsruhe Institute of Technology (KIT), Germany
Fabian Kempf, Karlsruhe Institute of Technology (KIT), Germany
Jurgen Becker, Karlsruhe Institute of Technology (KIT), Germany
Imen Baili, Menta eFPGA S.A.S., France |
15:15 |
Efficient
Autonomous Driving System Design: From Software to Hardware |
Yu Wang,
Tsinghgua University, China,
Kaiyuan Guo, Novauto Co. Ltd, China,
Xuefei Ning, Tsinghua University, China,
Yali Zhao, Tsinghua University China and Novauto Co. Ltd., China, Zhongyuan Qiu, Novauto Co.
Ltd., China,
Changcheng Tang, Novauto Co. Ltd., China,
Shuang Liang, Novauto Co. Ltd.,
China,
Huazhong Yang, Tsinghua University, China |
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Poster Session Details
Poster Session Details |
Session Chair: Panayiota Nicolaou, University of Cyprus, KIOS
Center of Excellence, Cyprus |
Time |
Poster
Title |
Authors |
14:45 |
Towards Everlasting Flash: Preventing Permanent Flash Cell
Damage Using Circadian Rhythms |
Muhammed Ceylan Morgul (University of Virgina, USA); Xinfei Guo
(Shanghai Jiao Tong University, China); Mircea Stan (University of Virginia,
USA) |
14:50 |
Hardware Emulation of FeFET on FPGA |
Paul-Antoine Matrangolo (University of Lyon, France & Ecole
Centrale de Lyon, INSA Lyon, CNRS, France); Cedric Marchand (Univ Lyon, Ecole
Centrale de Lyon, CNRS, INL, France); Ian O'Connor (Lyon Institute of
NanoTechnology & Ecole Centrale de Lyon, France); David Navarro (Ecole
Centrale de Lyon, France) |
14:55 |
Secure PUF-Based Authentication and Key Exchange Protocol Using
Machine Learning |
Amir Alipour (Université Grenoble Alpes, France); Fatemeh
Afghah (Clemson University, USA); David Hély (Grenoble INP - LCIS,
France); Vincent Beroulle (University of Grenoble Alpes, France); Giorgio Di
Natale (CNRS/TIMA, France) |
15:00 |
Optoelectronic Implementation of Compact and Power-Efficient
Recurrent Neural Networks |
Taisei Ichikawa, Tohru Ishihara and Yutaka Masuda (Nagoya
University, Japan); Akihiko Shinya and Masaya Notomi (NTT Nanophotonics
Center / Basic Research Laboratories, Japan) |
15:05 |
REFU: Redundant Execution With Idle Functional Units, Fault
Tolerant GPGPU Architecture |
Raghunandana K K and Varaprasad Bkslv (Indian Space Research
Organisation, India); Matteo Sonza Reorda (Politecnico di Torino, Italy);
Virendra Singh (Indian Institute of Technology Bombay, India) |
15:10 |
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance
for a Multicore Cluster |
Michael P Rogenmoser and Nils Wistoff (ETH Zurich, Switzerland);
Pirmin Vogel (ETH Zürich, Switzerland); Frank Gurkaynak and Luca Benini
(ETH Zurich, Switzerland) |
15:15 |
Exact Mapping of Quantum Circuit Partitions to Building Blocks
of the SAQIP Architecture |
Amirmohammad Biuki and Naser Mohammadzadeh (Shahed University,
Iran); Robert Wille (Technical University of Munich, Germany); Sahar Sargaran
(Shahed University, Iran) |
15:20 |
Possible Reductions to Generate Circuits From BDDs |
Eduarde D. Brandão (UFRGS, Brazil); João Paulo
Nespolo (Universidade Federal do Rio Grande do Sul, Brazil); Renato D.
Peralta (Federal University of Rio Grande do Sul, Brazil); Paulo F Butzen and
Andre I. Reis (UFRGS, Brazil) |
15:25 |
Accelerating NLP Tasks on FPGA With Compressed BERT and a
Hardware-Oriented Early Exit Method |
Binjing Li, Siyuan Lu, Keli Xie and Zhongfeng Wang (Nanjing
University, China) |
15:30 |
A New Hardware-Efficient VLSI-Architecture of GoogLeNet
CNN-Model Based Hardware Accelerator for Edge Computing Applications |
Rahul Shrestha (Indian Institute of Technology (IIT) Mandi,
India); Md Najrul Islam (IIT Mandi, India); Shubhajit Roy Chowdhury (School
of Computing and Electrical Engineering, IIT Mandi, India) |
15:35 |
A Permutation Challenge Input Interface for Arbiter PUF Variants
Against Machine Learning Attacks |
Yu Zhuang and Gaoxiang Li (Texas Tech University, USA); Khalid
Mursi (University of Jeddah, Saudi Arabia) |
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Student Poster Details
July 5th |
Student Posters |
Session Chair: Angeliki
Kritikakou, Université de Rennes 1, Inria, IRISA, CNRS, France |
Title |
Authors |
11:45 |
Accuracy Configurable FPGA Implementation of Harris Corner
Detection |
Shivani Maurya (IIIT Hyderabad, India); Ziaul Choudhury
(International Institute of Information Technology, Hyderabad, India); Suresh
Purini (IIIT Hyderabad, India) |
11:50 |
Designing Data-Aware Network-On-Chip for Performance |
Abhijit Das (INRIA, France); John Jose (Indian Institute of
Technology Guwahati, India) |
11:55 |
On the Detection and Circumvention of Bitstream-Level Trojans in
FPGAs |
Qazi Arbab Ahmed (Computer Engineering Group, Department of
Computer Science, Paderborn University, Germany) |
12:00 |
Architectural-Space Exploration of Energy-Efficient Approximate
Arithmetic Units for Error-Tolerant Applications |
Haroon Waris (Nanjing University of Aeronautics and Astronautics
(NUAA), China); Chenghua Wang and Weiqiang Liu (Nanjing University of
Aeronautics and Astronautics, China) |
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Research Demo Details
July 6th |
Research Demos |
Session Chair: Rafaella Elia, University of Cyprus |
Title |
Authors |
16:00 |
Securing
Hard Drives With the Security Protocol and Data Model (SPDM) |
Marcos A.
Simplicio Jr. (University of São Paulo, Brazil); Bruno C Albertini and
Renan C. A. Alves (Universidade de São Paulo, Brazil) |
16:05 |
Fall-Sense: An Enhanced Sensor System to Predict and Detect
Elderly Falls Using IoMT |
Laavanya Rachakonda and Daniel Marchand (University of North
Carolina Wilmington, USA) |
16:10 |
A Novel Approach to Quantum Circuit Partitioning |
Joseph Clark and Himanshu Thapliyal (University of Tennessee,
USA); Travis Humble (Oak Ridge National Laboratory, USA) |
16:15 |
MC-PUF: A Robust Lightweight Controlled Physical Unclonable
Function for Resource Constrained Environments |
Pintu Sadhu and Venkata Prasanth Yanambaka (Central Michigan
University, USA) |
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